//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================
#ifndef _BL_BULVERDE_H_
#define _BL_BULVERDE_H_

#ifndef LANGUAGE
# ifdef __ASSEMBLY__
#  define LANGUAGE Assembly
# else
#  define LANGUAGE C
#endif
#endif

//#include "bitfield.h"

#define C               0
#define Assembly        1

#if LANGUAGE == C
# define __REG(x) (*((volatile unsigned int *)(x)))
#else
# define __REG(x) (x)
#endif

/**********************************************************************/
/* MEMORY Address *****************************************************/
/**********************************************************************/
#define SDRAM_BASE_PHYSICAL 0xA0000000

/**********************************************************************
 * RELEVANT REGISTER-SPECIFIC OFFSETS
 **********************************************************************/
// MEMC
#define MEMC_BASE_PHYSICAL 0x48000000

#define MDCNFG_OFFSET        0x0
#define MDREFR_OFFSET        0x4
#define MSC0_OFFSET          0x8
#define MSC1_OFFSET          0xC
#define MSC2_OFFSET          0x10
#define MECR_OFFSET          0x14
#define SXCNFG_OFFSET        0x1C
#define FLYCNFG_OFFSET       0x20
#define MCMEM0_OFFSET        0x28
#define MCMEM1_OFFSET        0x2C
#define MCATT0_OFFSET        0x30
#define MCATT1_OFFSET        0x34
#define MCIO0_OFFSET         0x38
#define MCIO1_OFFSET         0x3C
#define MDMRS_OFFSET         0x40
#define BOOT_DEF_OFFSET      0x44
#define ARB_CNTL_OFFSET      0x48
#define BSCNTR0_OFFSET       0x4C
#define BSCNTR1_OFFSET       0x50
#define LCDBSCNTR_OFFSET     0x54
#define MDMRSLP_OFFSET       0x58
#define BSCNTR2_OFFSET       0x5C
#define BSCNTR3_OFFSET       0x60

// register bits for MEMC
#define MDCNFG_DE0           (1 << 0)
#define MDCNFG_DE1           (1 << 1)
#define MDCNFG_DWID0         (1 << 2)
#define MDCNFG_DCAC0         ( (1 << 3) + (1 << 4) )
#define MDCNFG_DRAC0         ( (1 << 5) + (1 << 6) )
#define MDCNFG_DNB0          (1 << 7)
#define MDCNFG_DTC0          ( (1 << 8) + (1 << 9) )
#define MDCNFG_DADDR0        (1 << 10)
#define MDCNFG_DLATCH0       (1 << 11)
#define MDCNFG_RESERVED0     ( (1 << 12) + (1 << 13) + (1 << 14) + (1 << 15) )
#define MDCNFG_DE2           (1 << 16)
#define MDCNFG_DE3           (1 << 17)
#define MDCNFG_DWID2         (1 << 18)
#define MDCNFG_DCAC2         ( (1 << 19) + (1 << 20) )
#define MDCNFG_DRAC2         ( (1 << 21) + (1 << 22) )
#define MDCNFG_DNB2          (1 << 23)
#define MDCNFG_DTC2          ( (1 << 24) + (1 << 25) )
#define MDCNFG_DADDR2        (1 << 26)
#define MDCNFG_DLATCH2       (1 << 27)
#define MDCNFG_RESERVED2     ( (1 << 28) + (1 << 29) + (1 << 30) + (1 << 31) )
#define MDREFR_E0PIN         0x00001000
#define MDREFR_K0RUN         0x00002000
#define MDREFR_K1RUN         0x00010000
#define MDREFR_K2RUN         0x00040000
#define MDREFR_SLFRSH        0x00400000
#define MDREFR_E1PIN         0x00008000
#define MDREFR_K1DB2         0x00020000      // run SDCLK[1] @ .5(MClk)
#define MDREFR_K0DB2         0x00004000
#define MDREFR_K0DB4         0x20000000      // run SDCLK[0] @ .25(MemClk)
#define MDREFR_K0FREE        0x00800000
#define MDREFR_K1FREE        0x01000000
#define MDREFR_K2FREE        0x02000000
#define MDREFR_APD           0x00100000
#define BANK_SHIFT           20

#if LANGUAGE == C
typedef unsigned short  Word16 ;
typedef unsigned int    Word32 ;
typedef Word32          Word ;
typedef Word            Quad [4] ;
typedef void            *Address ;
typedef void            (*ExcpHndlr) (void) ;
#endif

/******************************************************************/
/*   Peripheral OFFSETS                                           */
/******************************************************************/
#define DMAC_OFFSET     0x0             // DMA CONTROLLER
#define FFUART_OFFSET   0x00100000      // Full-Feature UART
#define BTUART_OFFSET   0x00200000      // BlueTooth UART
#define I2C_OFFSET      0x00300000      // I2C
#define I2S_OFFSET      0x00400000      // I2S
#define AC97_OFFSET     0x00500000      // AC97
#define UDC_OFFSET      0x00600000      // UDC (usb client)
#define STUART_OFFSET   0x00700000      // Standard UART
#define FIR_OFFSET      0x00800000      // FIR
#define RTC_OFFSET      0x00900000      // real time clock
#define OST_OFFSET      0x00A00000      // OS Timer
#define PWM0_2_OFFSET   0x00B00000      // PWM 0 (pulse-width mod)
#define PWM1_3_OFFSET   0x00C00000      // PWM 1 (pulse-width mod)
#define INTC_OFFSET     0x00D00000      // Interrupt controller
#define GPIO_OFFSET     0x00E00000      // GPIO
#define PWR_OFFSET      0x00F00000      // Power Manager and Reset Control
#define SSP1_OFFSET     0x01000000      // SSP 1
#define MMC_OFFSET      0x01100000      // MMC
#define CLK_OFFSET      0x01300000      // Clock Manager
#define BB_OFFSET       0x01400000      // Baseband Interface
#define KYPD_OFFSET     0x01500000      // Keypad Interface
#define USIM_OFFSET     0x01600000      // USIM
#define SSP2_OFFSET     0x01700000      // SSP 2
#define MEMSTK_OFFSET   0x01800000      // Memory Stick
#define SSP3_OFFSET     0x01900000      // SSP 3

////////////////////////////////////////////////////////////////////////
/* Peripheral-specific base addresses */
////////////////////////////////////////////////////////////////////////
#define PERIF_BASE_PHYSICAL 0x40000000
#define LCD_BASE_PHYSICAL 0x44000000

#define FFUART_BASE_PHYSICAL      (PERIF_BASE_PHYSICAL + FFUART_OFFSET)
#define BTUART_BASE_PHYSICAL      (PERIF_BASE_PHYSICAL + BTUART_OFFSET)
#define STUART_BASE_PHYSICAL      (PERIF_BASE_PHYSICAL + STUART_OFFSET)
#define RTC_BASE_PHYSICAL         (PERIF_BASE_PHYSICAL + RTC_OFFSET)
#define OST_BASE_PHYSICAL         (PERIF_BASE_PHYSICAL + OST_OFFSET)
#define INTC_BASE_PHYSICAL        (PERIF_BASE_PHYSICAL + INTC_OFFSET)
#define GPIO_BASE_PHYSICAL        (PERIF_BASE_PHYSICAL + GPIO_OFFSET)
#define PWR_BASE_PHYSICAL         (PERIF_BASE_PHYSICAL + PWR_OFFSET)
#define CLK_BASE_PHYSICAL         (PERIF_BASE_PHYSICAL + CLK_OFFSET)
#define I2C_BASE_PHYSICAL         (PERIF_BASE_PHYSICAL + I2C_OFFSET)

/*
 * UARTs
 */

/* Full Function UART (FFUART) */
#define FF_THR_OFFSET   0x0   //DLAB = 0  WO  8bit - Transmit Holding Register
#define FF_RBR_OFFSET   0x0   //DLAB = 0  RO  8bit - Recieve Buffer Register
#define FF_DLL_OFFSET   0x0   //DLAB = 1  RW  8bit - Divisor Latch Low Register
#define FF_IER_OFFSET   0x4   //DLAB = 0  RW  8bit - Interrupt Enable Register
#define FF_DLH_OFFSET   0x4   //DLAB = 1  RW  8bit - Divisor Latch High Register
#define FF_IIR_OFFSET   0x8   //DLAB = X  RO  8bit - Interrupt Identification Register
#define FF_FCR_OFFSET   0x8   //DLAB = X  WO  8bit - FIFO Control Register
#define FF_LCR_OFFSET   0xC   //DLAB = X  RW  8bit - Line Control Register
#define FF_MCR_OFFSET   0x10   //DLAB = X  RW  8bit - Modem Control Regiser
#define FF_LSR_OFFSET   0x14   //DLAB = X  RO  8bit - Line Status Register
#define FF_MSR_OFFSET   0x18   //DLAB = X  RO  8bit - Modem Status Register
#define FF_SPR_OFFSET   0x1C   //DLAB = X  RW  8bit - Scratchpad Register
#define FF_ISR_OFFSET   0x20   //DLAB = X  RW  8bit - Slow Infrared Select Register
#define FF_FOR_OFFSET   0x24   //DLAB = X  RO  FIFO Occupancy Register
#define FF_ABR_OFFSET   0x28   //DLAB = X  RW  Autobaud Control Register
#define FF_ACR_OFFSET   0x2C   //DLAB = X Autobaud Count Register

/* Bluetooth UART (BTUART) */
#define BT_THR_OFFSET   0x0   //DLAB = 0  WO  8bit - Transmit Holding Register
#define BT_RBR_OFFSET   0x0   //DLAB = 0  RO  8bit - Recieve Buffer Register
#define BT_DLL_OFFSET   0x0   //DLAB = 1  RW  8bit - Divisor Latch Low Register
#define BT_IER_OFFSET   0x4   //DLAB = 0  RW  8bit - Interrupt Enable Register
#define BT_DLH_OFFSET   0x4   //DLAB = 1  RW  8bit - Divisor Latch High Register
#define BT_IIR_OFFSET   0x8   //DLAB = X  RO  8bit - Interrupt Identification Register
#define BT_FCR_OFFSET   0x8   //DLAB = X  WO  8bit - FIFO Control Register
#define BT_LCR_OFFSET   0xC   //DLAB = X  RW  8bit - Line Control Register
#define BT_MCR_OFFSET   0x10   //DLAB = X  RW  8bit - Modem Control Regiser
#define BT_LSR_OFFSET   0x14   //DLAB = X  RO  8bit - Line Status Register
#define BT_MSR_OFFSET   0x18   //DLAB = X  RO  8bit - Modem Status Register
#define BT_SPR_OFFSET   0x1C   //DLAB = X  RW  8bit - Scratchpad Register
#define BT_ISR_OFFSET   0x20   //DLAB = X  RW  8bit - Slow Infrared Select Register
#define BT_FOR_OFFSET   0x24   //DLAB = X  RO  FIFO Occupancy Register
#define BT_ABR_OFFSET   0x28   //DLAB = X  RW  Autobaud Control Register
#define BT_ACR_OFFSET   0x2C   //DLAB = X Autobaud Count Register

/* Standard UART (STUART) */
#define ST_THR_OFFSET  0x0      //DLAB = 0  WO  8bit - Transmit Holding Register
#define ST_RBR_OFFSET  0x0      //DLAB = 0  RO  8bit - Recieve Buffer Register
#define ST_DLL_OFFSET  0x0      //DLAB = 1  RW  8bit - Divisor Latch Low Register
#define ST_IER_OFFSET  0x4      //DLAB = 0  RW  8bit - Interrupt Enable Register
#define ST_DLH_OFFSET  0x4      //DLAB = 1  RW  8bit - Divisor Latch High Register
#define ST_IIR_OFFSET  0x8      //DLAB = X  RO  8bit - Interrupt Identification Register
#define ST_FCR_OFFSET  0x8      //DLAB = X  WO  8bit - FIFO Control Register
#define ST_LCR_OFFSET  0xC      //DLAB = X  RW  8bit - Line Control Register
#define ST_MCR_OFFSET  0x10      //DLAB = X  RW  8bit - Modem Control Regiser
#define ST_LSR_OFFSET  0x14      //DLAB = X  RO  8bit - Line Status Register
#define ST_MSR_OFFSET  0x18      //DLAB = X  RO  8bit - Modem Status Register
#define ST_SPR_OFFSET  0x1C      //DLAB = X  RW  8bit - Scratchpad Register
#define ST_ISR_OFFSET  0x20      //DLAB = X  RW  8bit - Slow Infrared Select Register
#define ST_FOR_OFFSET  0x24      //DLAB = X  RO  FIFO Occupancy Register
#define ST_ABR_OFFSET  0x28      //DLAB = X  RW  Autobaud Control Register
#define ST_ACR_OFFSET  0x2C      //DLAB = X Autobaud Count Register

#define IER_DMAE (1 << 7) /* DMA Requests Enable */
#define IER_UUE  (1 << 6) /* UART Unit Enable */
#define IER_NRZE (1 << 5) /* NRZ coding Enable */
#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
#define IER_MIE  (1 << 3) /* Modem Interrupt Enable */
#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
#define IER_TIE  (1 << 1) /* Transmit Data request Interrupt Enable */
#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */

#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
#define IIR_TOD  (1 << 3) /* Time Out Detected */
#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
#define IIR_IP  (1 << 0) /* Interrupt Pending (active low) */

#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
#define FCR_ITL_1 (0)
#define FCR_ITL_8 (FCR_ITL1)
#define FCR_ITL_16 (FCR_ITL2)
#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)

#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
#define LCR_SB  (1 << 6) /* Set Break */
#define LCR_STKYP (1 << 5) /* Sticky Parity */
#define LCR_EPS  (1 << 4) /* Even Parity Select */
#define LCR_PEN  (1 << 3) /* Parity Enable */
#define LCR_STB  (1 << 2) /* Stop Bit */
#define LCR_WLS1 (1 << 1) /* Word Length Select */
#define LCR_WLS0 (1 << 0) /* Word Length Select */

#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
#define LSR_TEMT (1 << 6) /* Transmitter Empty */
#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
#define LSR_BI  (1 << 4) /* Break Interrupt */
#define LSR_FE  (1 << 3) /* Framing Error */
#define LSR_PE  (1 << 2) /* Parity Error */
#define LSR_OE  (1 << 1) /* Overrun Error */
#define LSR_DR  (1 << 0) /* Data Ready */

#define MCR_LOOP (1 << 4) /* */
#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
#define MCR_RTS  (1 << 1) /* Request to Send */
#define MCR_DTR  (1 << 0) /* Data Terminal Ready */

#define MSR_DCD  (1 << 7) /* Data Carrier Detect */
#define MSR_RI  (1 << 6) /* Ring Indicator */
#define MSR_DSR  (1 << 5) /* Data Set Ready */
#define MSR_CTS  (1 << 4) /* Clear To Send */
#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
#define MSR_DCTS (1 << 0) /* Delta Clear To Send */

/*
 * Real Time Clock
 */
#define RCNR_OFFSET       0x0      //RTC count register
#define RTAR_OFFSET       0x4      //RTC alarm register
#define RTSR_OFFSET       0x8      //RTC status register
#define RTTR_OFFSET       0xC      //RTC timer trim register
#define RDCR_OFFSET       0x10     //RTC Day Counter
#define RYCR_OFFSET       0x14     //RTC Year Counter
#define RDAR1_OFFSET      0x18     //RTC Day Alarm 1
#define RYAR1_OFFSET      0x1C     //RTC Year Alarm 1
#define RDAR2_OFFSET      0x20     //RTC Day Alarm 2
#define RYAR2_OFFSET      0x24     //RTC Year Alarm 2
#define SWCR_OFFSET       0x28     //RTC Stopwatch Counter
#define SWAR1_OFFSET      0x2C     //RTC Stopwatch Alarm 1
#define SWAR2_OFFSET      0x30     //RTC Stopwatch Alarm 2
#define PICR_OFFSET       0x34     //RTC Periodic Interrupt Counter
#define PIAR_OFFSET       0x38     //RTC Periodic Interrupt Alarm

#define RTSR_HZE        (1 << 3)        /* HZ interrupt enable */
#define RTSR_ALE        (1 << 2)        /* RTC alarm interrupt enable */
#define RTSR_HZ         (1 << 1)        /* HZ rising-edge detected */
#define RTSR_AL         (1 << 0)        /* RTC alarm detected */

/*
 * OS Timer & Match Registers
 */
#define OSMR0_OFFSET      0x0      //OS timer match register 0
#define OSMR1_OFFSET      0x4      //OS timer match register 1
#define OSMR2_OFFSET      0x8      //OS timer match register 2
#define OSMR3_OFFSET      0xC      //OS timer match register 3
#define OSCR0_OFFSET      0x10      //OS timer counter register 0
#define OSSR_OFFSET       0x14      //OS timer status register
#define OWER_OFFSET       0x18      //OS timer watchdog enable register
#define OIER_OFFSET       0x1C      //OS timer interrupt enable register
#define OSCR4_OFFSET      0x40
#define OSCR5_OFFSET      0x44
#define OSCR6_OFFSET      0x48
#define OSCR7_OFFSET      0x4C
#define OSCR8_OFFSET      0x50
#define OSCR9_OFFSET      0x54
#define OSCR10_OFFSET     0x58
#define OSCR11_OFFSET     0x5C
#define OSMR4_OFFSET      0x80
#define OSMR5_OFFSET      0x84
#define OSMR6_OFFSET      0x88
#define OSMR7_OFFSET      0x8C
#define OSMR8_OFFSET      0x90
#define OSMR9_OFFSET      0x94
#define OSMR10_OFFSET     0x98
#define OSMR11_OFFSET     0x9C
#define OMCR4_OFFSET      0xC0
#define OMCR5_OFFSET      0xC4
#define OMCR6_OFFSET      0xC8
#define OMCR7_OFFSET      0xCC
#define OMCR8_OFFSET      0xD0
#define OMCR9_OFFSET      0xD4
#define OMCR10_OFFSET     0xD8
#define OMCR11_OFFSET     0xDC

#define OIER_E7         (1 << 7)        /* Interrupt enable channel 7 */
#define OIER_E6         (1 << 6)        /* Interrupt enable channel 6 */
#define OIER_E5         (1 << 5)        /* Interrupt enable channel 5 */
#define OIER_E4         (1 << 4)        /* Interrupt enable channel 4 */
#define OIER_E3         (1 << 3)        /* Interrupt enable channel 3 */
#define OIER_E2         (1 << 2)        /* Interrupt enable channel 2 */
#define OIER_E1         (1 << 1)        /* Interrupt enable channel 1 */
#define OIER_E0         (1 << 0)        /* Interrupt enable channel 0 */

#define OSSR_M7         (1 << 7)        /* Match status channel 7 */
#define OSSR_M6         (1 << 6)        /* Match status channel 6 */
#define OSSR_M5         (1 << 5)        /* Match status channel 5 */
#define OSSR_M4         (1 << 4)        /* Match status channel 4 */
#define OSSR_M3         (1 << 3)        /* Match status channel 3 */
#define OSSR_M2         (1 << 2)        /* Match status channel 2 */
#define OSSR_M1         (1 << 1)        /* Match status channel 1 */
#define OSSR_M0         (1 << 0)        /* Match status channel 0 */

#define ICMR            __REG( INTC_BASE_PHYSICAL + ICMR_OFFSET )

/*
 * Interrupt Controller
 */
#define ICIP_OFFSET    0x0      //Interrupt controller IRQ pending register
#define ICMR_OFFSET    0x4      //Interrupt controller mask register
#define ICLR_OFFSET    0x8      //Interrupt controller level register
#define ICFP_OFFSET    0xC      //Interrupt controller FIQ pending register
#define ICPR_OFFSET    0x10     //Interrupt controller pending register
#define ICCR_OFFSET    0x14     //Interrupt controller control register
#define ICHP_OFFSET    0x18     //Interrupt controller Highest Priority register
#define IPR0_OFFSET    0x1C     //Interrupt controller Priority registerS [31:0]
#define IPR1_OFFSET    0x20
#define IPR2_OFFSET    0x24
#define IPR3_OFFSET    0x28
#define IPR4_OFFSET    0x2C
#define IPR5_OFFSET    0x30
#define IPR6_OFFSET    0x34
#define IPR7_OFFSET    0x38
#define IPR8_OFFSET    0x3C
#define IPR9_OFFSET    0x40
#define IPR10_OFFSET   0x44
#define IPR11_OFFSET   0x48
#define IPR12_OFFSET   0x4C
#define IPR13_OFFSET   0x50
#define IPR14_OFFSET   0x54
#define IPR15_OFFSET   0x58
#define IPR16_OFFSET   0x5C
#define IPR17_OFFSET   0x60
#define IPR18_OFFSET   0x64
#define IPR19_OFFSET   0x68
#define IPR20_OFFSET   0x6C
#define IPR21_OFFSET   0x70
#define IPR22_OFFSET   0x74
#define IPR23_OFFSET   0x78
#define IPR24_OFFSET   0x7C
#define IPR25_OFFSET   0x80
#define IPR26_OFFSET   0x84
#define IPR27_OFFSET   0x88
#define IPR28_OFFSET   0x8C
#define IPR29_OFFSET   0x90
#define IPR30_OFFSET   0x94
#define IPR31_OFFSET   0x98

#define ICMR2_OFFSET    0xA0      //Interrupt controller mask register 2
#define ICLR2_OFFSET    0xA4      //Interrupt controller level register 2

/* IRQ bit setting  */
#define IRQ_SSP3 (1 << 0) /* SSP3 */
#define IRQ_MSL  (1 << 1) /* MSL */
#define IRQ_USB_HOST2 (1 << 2) /* USB HOST 2*/
#define IRQ_USB_HOST1 (1 << 3) /* USB HOST 1*/
#define IRQ_KEYPAD (1 << 4) /* Keypad */
#define IRQ_MEM_STICK (1 << 5) /* Memory Stick */
#define IRQ_PWR_I2C (1 << 6) /* Power Control I2C */
#define IRQ_OST_4_11 (1 << 7) /* OS Timer 4-11*/
#define IRQ_GPIO0 (1 << 8) /* GPIO0 Edge Detect */
#define IRQ_GPIO1 (1 << 9) /* GPIO1 Edge Detect */
#define IRQ_GPIO_2_118 (1 << 10) /* GPIO[2-118] Edge Detect */
#define IRQ_USB_DEVICE (1 << 11) /* USB Service */
#define IRQ_PMU  (1 << 12) /* Performance Monitoring Unit */
#define IRQ_I2S  (1 << 13) /* I2S Interrupt */
#define IRQ_AC97 (1 << 14) /* AC97 Interrupt */
#define IRQ_USIM (1 << 15) /* USIM */
#define IRQ_SSP2 (1 << 16) /* SSP2*/
#define IRQ_LCD  (1 << 17) /* LCD Controller Service Request */
#define IRQ_I2C  (1 << 18) /* I2C Service Request */
#define IRQ_ICP  (1 << 19) /* ICP Transmit/Receive/Error */
#define IRQ_STUART (1 << 20) /* STUART Transmit/Receive/Error */
#define IRQ_BTUART (1 << 21) /* BTUART Transmit/Receive/Error */
#define IRQ_FFUART (1 << 22) /* FFUART Transmit/Receive/Error*/
#define IRQ_MMC  (1 << 23) /* MMC Status/Error Detection */
#define IRQ_SSP1 (1 << 24) /* SSP1 Service Request */
#define IRQ_DMA  (1 << 25) /* DMA Channel Service Request */
#define IRQ_OST0 (1 << 26) /* OS Timer match 0 */
#define IRQ_OST1 (1 << 27) /* OS Timer match 1 */
#define IRQ_OST2 (1 << 28) /* OS Timer match 2 */
#define IRQ_OST3 (1 << 29) /* OS Timer match 3 */
#define IRQ_RTC_HZ (1 << 30) /* RTC HZ Clock Tick */
#define IRQ_RTC_AL (1 << 31) /* RTC Alarm */

/*
 * Power Manager
 */
#define PMCR_OFFSET     0x0  //Power manager control register
#define PSSR_OFFSET     0x4  //Power manager sleep status register
#define PSPR_OFFSET     0x8  //Power manager scratch pad register
#define PWER_OFFSET     0xC  //Power manager wake-up enable register
#define PRER_OFFSET     0x10  //Power manager GPIO rising edge detect enable register
#define PFER_OFFSET     0x14  //Power manager GPIO falling edge detect enable register
#define PEDR_OFFSET     0x18  //Power manager GPIO edge detect status register
#define PCFR_OFFSET     0x1C  //Power manager general configuration register
#define PGSR0_OFFSET    0x20  //Power manager GPIO sleep state register for GPIO 31:0
#define PGSR1_OFFSET    0x24  //Power manager GPIO sleep state register for GPIO 63:32
#define PGSR2_OFFSET    0x28  //Power manager GPIO sleep state register for GPIO 95:64
#define PGSR3_OFFSET    0x2C  //Power manager GPIO sleep state register for GPIO 120:96
#define RCSR_OFFSET     0x30  // **Reset controller status register**
#define PSLR_OFFSET     0x34  //Power manager Sleep Mode Config
#define PSTR_OFFSET     0x38  //Power manager Standby Mode Config
#define PSNR_OFFSET     0x3C  //Power manager Sense Mode Config
#define PVCR_OFFSET     0x40  //Power manager Voltage Change Control
#define PCMD0_OFFSET    0x80  //Power manager I2C Command[31:0]
#define PCMD1_OFFSET    0x84
#define PCMD2_OFFSET    0x88
#define PCMD3_OFFSET    0x8C
#define PCMD4_OFFSET    0x90
#define PCMD5_OFFSET    0x94
#define PCMD6_OFFSET    0x98
#define PCMD7_OFFSET    0x9C
#define PCMD8_OFFSET    0xA0
#define PCMD9_OFFSET    0xA4
#define PCMD10_OFFSET   0xA8
#define PCMD11_OFFSET   0xAC
#define PCMD12_OFFSET   0xB0
#define PCMD13_OFFSET   0xB4
#define PCMD14_OFFSET   0xB8
#define PCMD15_OFFSET   0xBC
#define PCMD16_OFFSET   0xC0
#define PCMD17_OFFSET   0xC4
#define PCMD18_OFFSET   0xC8
#define PCMD19_OFFSET   0xCC
#define PCMD20_OFFSET   0xD0
#define PCMD21_OFFSET   0xD4
#define PCMD22_OFFSET   0xD8
#define PCMD23_OFFSET   0xDC
#define PCMD24_OFFSET   0xE0
#define PCMD25_OFFSET   0xE4
#define PCMD26_OFFSET   0xE8
#define PCMD27_OFFSET   0xEC
#define PCMD28_OFFSET   0xF0
#define PCMD29_OFFSET   0xF4
#define PCMD30_OFFSET   0xF8
#define PCMD31_OFFSET   0xFC
#define PIBMR_OFFSET    0x180     //Power manager I2C Bus Monitor
#define PIDBR_OFFSET    0x188     //Power manager I2C Data Buffer
#define PI2CR_OFFSET    0x190     //Power manager I2C Control
#define PISR_OFFSET     0x198     //Power manager I2C Status
#define PISAR_OFFSET    0x1A0     //Power manager I2C Slave Address
#define IBMR_OFFSET    0x1680     //I2C Bus Monitor
#define IDBR_OFFSET    0x1688     //I2C Data Buffer
#define I2CR_OFFSET    0x1690     //I2C Control
#define ISR_OFFSET     0x1698     //I2C Status
#define ISAR_OFFSET    0x16A0     //I2C Slave Address

/********* Power manager module bit values ***********************/

// Reset Controller Status Register bit defines
#define RCSR_HARD_RESET    (0x1)
#define RCSR_WDOG_RESET    (0x1 << 1)
#define RCSR_SLEEP_RESET   (0x1 << 2)
#define RCSR_GPIO_RESET    (0x1 << 3)
#define PSSR_VALID_MASK    0x3F
#define PSSR_RDH           (0x1 << 5)
#define PSSR_PH            (0x1 << 4)

#if 1
#define RCSR_ALL       0x0F
#else
#define RCSR_ALL       0x1F    // bman: EAS 1.5 is a bit unclear; is bit 4 reserved or no t? If so, then this value should be 0xF
#endif

// Power Manager Defs
#define PCFR_OPDE      (0x1)
#define PCFR_FP        (0x1 << 1)
#define PCFR_FS        (0x1 << 2)
#define PCFR_GPR_EN    (0x1 << 4)
#define PCFR_SYSEN_EN  (0x1 << 5)
#define PCFR_PI2C_EN   (0x1 << 6)
#define PCFR_DC_EN     (0x1 << 7)
#define PCFR_FVC       (0x1 << 10)
#define PCFR_L1_EN     (0x1 << 11)
#define PCFR_GP_ROD    (0x1 << 12)
#define PWER_WE0       (0x1)
#define PWER_WE1       (0x1 << 1)
#define PWER_WBB       (0x1 << 25)
#define PWER_WEUSBC    (0x1 << 26)
#define PWER_WEUSBH0   (0x1 << 27)
#define PWER_WEUSBH1   (0x1 << 28)
#define PWER_WEP1      (0x1 << 30)
#define PWER_WERTC     (0x1 << 31)
#define PMCR_BIDAE     (0x1)
#define PMCR_BIDAS     (0x1 << 1)
#define PMCR_VIDAE     (0x1 << 2)
#define PMCR_VIDAS     (0x1 << 3)
#define PMCR_IAS       (0x1 << 4)
#define PMCR_INTRS     (0x1 << 5)

/*
 * Core Clock
 */
#define OSCC  __REG(0x41300008)
#define CCCR_OFFSET   0x0      //Core Clock Configuration Register
#define CKEN_OFFSET   0x4      //Clock Enable Register
#define OSCC_OFFSET   0x8      //Oscillator Configuration Register
#define CCSR_OFFSET   0xC      //Core Clock Status

#define OSCC_OOK       (0x1 << 0)
#define OSCC_OON       (0x1 << 1)
#define OSCC_TOUT_EN   (0x1 << 2)
#define OSCC_PIO_EN    (0x1 << 3)
#define OSCC_CRI       (0x1 << 4)
#define CKEN_DEFAULT   0x00400280     // MEMC, OST, FFUART clocked.  Rest OFF

#define CKEN23_CAMERA (1 << 16) /* CAMERA Unit Clock Enable */
#define CKEN24_SSP1 (1 << 16) /* SSP1 Unit Clock Enable */
#define CKEN22_MEMCTL (1 << 16) /* Memory Controller Unit Clock Enable */
#define CKEN21_MEMSTICK (1 << 16) /* Memory Stick Unit Clock Enable */
#define CKEN20_IN_MEM (1 << 16) /* Internal Memory Unit Clock Enable */
#define CKEN19_KEYPAD (1 << 16) /* Key Pad Unit Clock Enable */
#define CKEN18_USIM (1 << 16) /* USIM Unit Clock Enable */
#define CKEN17_MSL (1 << 16) /* MSL Unit Clock Enable */
#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */
#define CKEN15_PM_I2C (1 << 16) /* Power Manager I2C Unit Clock Enable */
#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */
#define CKEN13_ICP (1 << 13) /* ICP Unit Clock Enable */
#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
#define CKEN11_USBDEV (1 << 11) /* USB Client Clock Enable */
#define CKEN10_USBHOST (1 << 8) /* USB HOST Unit Clock Enable */
#define CKEN9_OST (1 << 8) /* OST Unit Clock Enable */
#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */
#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
#define CKEN4_SSP3 (1 << 5) /* SSP3 Unit Clock Enable */
#define CKEN3_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */
#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */
#define CKEN1_PWM1_3 (1 << 1) /* PWM1, PWM3 Clock Enable */
#define CKEN0_PWM0_2 (1 << 0) /* PWM0, PWM2 Clock Enable */

/*
 * LCD Controller
 */
#define LCD_LCCR0 0x44000000
#define LCD_LCCR1 0x44000004
#define LCD_LCCR2 0x44000008
#define LCD_LCCR3 0x4400000C

/*
 *
 */
#define FRAMEBUFFER (0xa0000000 + 0x04000000 - 1024*1024*1 - 320*240*2)

#define DMA_FFADDR0 0X44000200

/*
 * General Purpose I/O
 */
#define GPLR0_OFFSET     0x0      //GPIO pin-level register 31:0
#define GPLR1_OFFSET     0x4      //GPIO pin-level register 63:32
#define GPLR2_OFFSET     0x8      //GPIO pin-level register 95:64
#define GPDR0_OFFSET     0xC      //GPIO pin-direction register 31:0
#define GPDR1_OFFSET     0x10     //GPIO pin-direction register 63:32
#define GPDR2_OFFSET     0x14     //GPIO pin-direction register 95:64
#define GPSR0_OFFSET     0x18     //GPIO pin output set register 31:0
#define GPSR1_OFFSET     0x1C     //GPIO pin output set register 63:32
#define GPSR2_OFFSET     0x20     //GPIO pin output set register 95:64
#define GPCR0_OFFSET     0x24     //GPIO pin output clear register 31:0
#define GPCR1_OFFSET     0x28     //GPIO pin output clear register 63:32
#define GPCR2_OFFSET     0x2C     //GPIO pin output clear register 95:64
#define GRER0_OFFSET     0x30     //GPIO rising edge detect register 31:0
#define GRER1_OFFSET     0x34     //GPIO rising edge detect register 63:32
#define GRER2_OFFSET     0x38     //GPIO rising edge detect register 95:64
#define GFER0_OFFSET     0x3C     //GPIO falling edge detect register 31:0
#define GFER1_OFFSET     0x40     //GPIO falling edge detect register 63:32
#define GFER2_OFFSET     0x44     //GPIO falling edge detect register 95:64
#define GEDR0_OFFSET     0x48     //GPIO edge detect status register 31:0
#define GEDR1_OFFSET     0x4C     //GPIO edge detect status register 63:32
#define GEDR2_OFFSET     0x50     //GPIO edge detect status register 95:64
#define GAFR0_L_OFFSET   0x54     //GPIO alternate funciton select register 15:0
#define GAFR0_U_OFFSET   0x58     //GPIO alternate function select register 31:16
#define GAFR1_L_OFFSET   0x5C     //GPIO alternate function select register 47:32
#define GAFR1_U_OFFSET   0x60     //GPIO alternate function select register 63:48
#define GAFR2_L_OFFSET   0x64     //GPIO alternate function select register 79:64
#define GAFR2_U_OFFSET   0x68     //GPIO alternate function select register 95:80
#define GAFR3_L_OFFSET   0x6C     //GPIO alternate function select register 111:96
#define GAFR3_U_OFFSET   0x70     //GPIO alternate function select register 120:112
#define GPLR3_OFFSET     0x100    //GPIO pin-level register 120:96
#define GPDR3_OFFSET     0x10C    //GPIO pin-direction register 120:96
#define GPSR3_OFFSET     0x118    //GPIO pin output set register 120:96
#define GPCR3_OFFSET     0x124    //GPIO pin output clear register 120:96
#define GRER3_OFFSET     0x130    //GPIO rising edge detect register 120:96
#define GFER3_OFFSET     0x13C    //GPIO falling edge detect register 120:96
#define GEDR3_OFFSET     0x148    //GPIO edge detect status register 120:96

#define GPLR0       __REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
#define GPLR1       __REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
#define GPLR2       __REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */

#define GPDR0       __REG(0x40E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */
#define GPDR1       __REG(0x40E00010)  /* GPIO Pin Direction Register GPIO<63:32> */
#define GPDR2       __REG(0x40E00014)  /* GPIO Pin Direction Register GPIO<80:64> */

#define GPSR0       __REG(0x40E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */
#define GPSR1       __REG(0x40E0001C)  /* GPIO Pin Output Set Register GPIO<63:32> */
#define GPSR2       __REG(0x40E00020)  /* GPIO Pin Output Set Register GPIO<80:64> */

#define GPCR0       __REG(0x40E00024)  /* GPIO Pin Output Clear Register GPIO<31:0> */
#define GPCR1       __REG(0x40E00028)  /* GPIO Pin Output Clear Register GPIO <63:32> */
#define GPCR2       __REG(0x40E0002C)  /* GPIO Pin Output Clear Register GPIO <80:64> */

#define GRER0       __REG(0x40E00030)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
#define GRER1       __REG(0x40E00034)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
#define GRER2       __REG(0x40E00038)  /* GPIO Rising-Edge Detect Register GPIO<80:64> */

#define GFER0       __REG(0x40E0003C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
#define GFER1       __REG(0x40E00040)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
#define GFER2       __REG(0x40E00044)  /* GPIO Falling-Edge Detect Register GPIO<80:64> */

#define GEDR0       __REG(0x40E00048)  /* GPIO Edge Detect Status Register GPIO<31:0> */
#define GEDR1       __REG(0x40E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */
#define GEDR2       __REG(0x40E00050)  /* GPIO Edge Detect Status Register GPIO<80:64> */

#define GAFR0_L     __REG(0x40E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */
#define GAFR0_U     __REG(0x40E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */
#define GAFR1_L     __REG(0x40E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */
#define GAFR1_U     __REG(0x40E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */
#define GAFR2_L     __REG(0x40E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */
#define GAFR2_U     __REG(0x40E00068)  /* GPIO Alternate Function Select Register GPIO 80 */
#define GAFR3_L     __REG(0x40E0006C)  /* GPIO Alternate Function Select Register GPIO<96-111>*/
#define GAFR3_U     __REG(0x40E00070)  /* GPIO Alternate Function Select Register GPIO<112-127>*/
#define GPLR3       __REG(0x40E00100)  /* GPIO Pin-Level Register GPIO<127:96> */
#define GPDR3       __REG(0x40E0010C)  /* GPIO Pin Direction Register GPIO<127:96> */
#define GPSR3       __REG(0x40E00118)  /* GPIO Pin Output Set Register GPIO<127:96> */
#define GPCR3       __REG(0x40E00124)  /* GPIO Pin Output Clear Register GPIO<127:96> */
#define GRER3       __REG(0x40E00130)  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
#define GEDR3       __REG(0x40E00148)  /* GPIO Edge Detect Status Register GPIO<127:96> */

/***********************************************************/
/* GPIO Alternating Function Settings (GAFR[0;1;2;3]_[L;U])*/
/***********************************************************/
/* 
 * GAFR0_L (gpio[15:0]) 
 */
/* AF1 */
#define GPIO_0_AF1                      (0x1 << 0)
#define GPIO_1_AF1                      (0x1 << 2)
#define GPIO_2_AF1                      (0x1 << 4)
#define GPIO_3_AF1                      (0x1 << 6)
#define GPIO_4_AF1                      (0x1 << 8)
#define GPIO_5_AF1                      (0x1 << 10)
#define GPIO_6_AF1                      (0x1 << 12)
#define GPIO_7_AF1                      (0x1 << 14)
#define GPIO_8_AF1                      (0x1 << 16)
#define GPIO_9_AF1_HZCLK                (0x1 << 18)
#define GPIO_10_AF1_HZCLK               (0x1 << 20)
#define GPIO_11_AF1_EXTSYNC0_CHOUT0     (0x1 << 22)
#define GPIO_12_AF1_EXTSYNC1_CHOUT1     (0x1 << 24)
#define GPIO_13_AF1_CLKEXT              (0x1 << 26)
#define GPIO_14_AF1_LVSYNC              (0x1 << 28)
#define GPIO_15_AF1_PCMCIAnPCE1         (0x1 << 30)

/* AF2 */
#define GPIO_0_AF2            (0x2 << 0)
#define GPIO_1_AF2            (0x2 << 2)
#define GPIO_2_AF2            (0x2 << 4)
#define GPIO_3_AF2            (0x2 << 6)
#define GPIO_4_AF2            (0x2 << 8)
#define GPIO_5_AF2            (0x2 << 10)
#define GPIO_6_AF2            (0x2 << 12)
#define GPIO_7_AF2            (0x2 << 14)
#define GPIO_8_AF2            (0x2 << 16)
#define GPIO_9_AF2            (0x2 << 18)
#define GPIO_10_AF2           (0x2 << 20)
#define GPIO_11_AF2_PWMOUT2   (0x2 << 22)
#define GPIO_12_AF2_PWMOUT3   (0x2 << 24)
#define GPIO_13_AF2_KPDKIN7   (0x2 << 26)
#define GPIO_14_AF2           (0x2 << 28)
#define GPIO_15_AF2_nCS1      (0x2 << 30)

/* AF3 */
#define GPIO_0_AF3            (0x3 << 0)
#define GPIO_1_AF3            (0x3 << 2)
#define GPIO_2_AF3            (0x3 << 4)
#define GPIO_3_AF3            (0x3 << 6)
#define GPIO_4_AF3            (0x3 << 8)
#define GPIO_5_AF3            (0x3 << 10)
#define GPIO_6_AF3            (0x3 << 12)
#define GPIO_7_AF3            (0x3 << 14)
#define GPIO_8_AF3            (0x3 << 16)
#define GPIO_9_AF3_CHOUT0     (0x3 << 18)
#define GPIO_10_AF3_CHOUT1    (0x3 << 20)
#define GPIO_11_AF3_48MCLK    (0x3 << 22)
#define GPIO_12_AF3_48MCLK    (0x3 << 24)
#define GPIO_13_AF3_KPMKIN7   (0x3 << 26)
#define GPIO_14_AF3           (0x3 << 28)
#define GPIO_15_AF3           (0x3 << 30)

/* 
 * GAFR0_U (gpio[31:16]) 
 */
/* AF1 */
#define GPIO_16_AF1_KPMKIN5                 (0x1 << 0)
#define GPIO_17_AF1_KPMKIN6                 (0x1 << 2)
#define GPIO_18_AF1_RDY                     (0x1 << 4)
#define GPIO_19_AF1                         (0x1 << 6)
#define GPIO_20_AF1_DREQ0_nSDCS2            (0x1 << 8)
#define GPIO_21_AF1_nSDCS3                  (0x1 << 10)
#define GPIO_22_AF1_SSPEXTCLK2_KPMKOUT7 EQU (0x1 << 12)
#define GPIO_23_AF1                         (0x1 << 14)
#define GPIO_24_AF1                         (0x1 << 16)
#define GPIO_25_AF1                         (0x1 << 18)
#define GPIO_26_AF1_SSPRXD                  (0x1 << 20)
#define GPIO_27_AF1_SSPEXTCLK               (0x1 << 22)
#define GPIO_28_AF1_AC97_I2S_BITCLK         (0x1 << 24)
#define GPIO_29_AF1_AC97SDATAIN0            (0x1 << 26)
#define GPIO_30_AF1_I2SSDATAOUT             (0x1 << 28)
#define GPIO_31_AF1_I2SSYNC                 (0x1 << 30)

/* AF2 */
#define GPIO_16_AF2_PWMOUT0       (0x2 << 0)
#define GPIO_17_AF2_PWMOUT1       (0x2 << 2)
#define GPIO_18_AF2               (0x2 << 4)
#define GPIO_19_AF2_LCS           (0x2 << 6)
#define GPIO_20_AF2_MBREQ         (0x2 << 8)
#define GPIO_21_AF2_DVAL0         (0x2 << 10)
#define GPIO_22_AF2_SSPSCLK2EN    (0x2 << 12)
#define GPIO_23_AF2_SSPSCLK       (0x2 << 14)
#define GPIO_24_AF2_SSPSFRM       (0x2 << 16)
#define GPIO_25_AF2_SSPTXD        (0x2 << 18)
#define GPIO_26_AF2               (0x2 << 20)
#define GPIO_27_AF2_SSPSCLKEN     (0x2 << 22)
#define GPIO_28_AF2_I2SBITCLK     (0x2 << 24)
#define GPIO_29_AF2_I2SSDATAIN    (0x2 << 26)
#define GPIO_30_AF2_AC97SDATAOUT  (0x2 << 28)
#define GPIO_31_AF2_AC97SYNC      (0x2 << 30)

/* AF3 */
#define GPIO_16_AF3             (0x3 << 0)
#define GPIO_17_AF3             (0x3 << 2)
#define GPIO_18_AF3             (0x3 << 4)
#define GPIO_19_AF3             (0x3 << 6)
#define GPIO_20_AF3             (0x3 << 8)
#define GPIO_21_AF3_MBGNT       (0x3 << 10)
#define GPIO_22_AF3             (0x3 << 12)
#define GPIO_23_AF3             (0x3 << 14)
#define GPIO_24_AF3             (0x3 << 16)
#define GPIO_25_AF3             (0x3 << 18)
#define GPIO_26_AF3             (0x3 << 20)
#define GPIO_27_AF3             (0x3 << 22)
#define GPIO_28_AF3             (0x3 << 24)
#define GPIO_29_AF3             (0x3 << 26)
#define GPIO_30_AF3             (0x3 << 28)
#define GPIO_31_AF3             (0x3 << 30)

/* 
 * GAFR1_L (gpio[47:31]) 
 */
/* AF1 */
#define GPIO_32_AF1_MSSCLK           (0x1 << 0)
#define GPIO_33_AF1_DVAL1            (0x1 << 2)
#define GPIO_34_AF1_FFRXD            (0x1 << 4)
#define GPIO_35_AF1_FFCTS            (0x1 << 6)
#define GPIO_36_AF1_FFDCD            (0x1 << 8)
#define GPIO_37_AF1_FFDSR            (0x1 << 10)
#define GPIO_38_AF1_FFRI             (0x1 << 12)
#define GPIO_39_AF1_KPMKIN4          (0x1 << 14)
#define GPIO_40_AF1_SSPRXD2_KPMKOUT6 (0x1 << 16)
#define GPIO_41_AF1_KPMKOUT7         (0x1 << 18)
#define GPIO_42_AF1_BTRXD            (0x1 << 20)
#define GPIO_43_AF1_ICPTXD           (0x1 << 22)
#define GPIO_44_AF1_BTCTS            (0x1 << 24)
#define GPIO_45_AF1_AC97SYSCLK       (0x1 << 26)
#define GPIO_46_AF1_ICPRXD           (0x1 << 28)
#define GPIO_47_AF1_STDTXD           (0x1 << 30)

/* AF2 */
#define GPIO_32_AF2_MMCLK            (0x2 << 0)
#define GPIO_33_AF2_nCS5             (0x2 << 2)
#define GPIO_34_AF2_KPMKIN3          (0x2 << 4)
#define GPIO_35_AF2_KPMKOUT6         (0x2 << 6)
#define GPIO_36_AF2_SSPSCLK2         (0x2 << 8)
#define GPIO_37_AF2_SSPSFRM2         (0x2 << 10)
#define GPIO_38_AF2_KPMKIN4_SSPTXD2  (0x2 << 12)
#define GPIO_39_AF2_FFTXD            (0x2 << 14)
#define GPIO_40_AF2_FFDTR            (0x2 << 16)
#define GPIO_41_AF2_FFRTS            (0x2 << 18)
#define GPIO_42_AF2_ICPRXD           (0x2 << 20)
#define GPIO_43_AF2_BTTXD            (0x2 << 22)
#define GPIO_44_AF2                  (0x2 << 24)
#define GPIO_45_AF2_BTRTS            (0x2 << 26)
#define GPIO_46_AF2_STDRXD_PWMOUT2   (0x2 << 28)
#define GPIO_47_AF2_ICPTXD           (0x2 << 30)

/* AF3 */
#define GPIO_32_AF3                  (0x3 << 0)
#define GPIO_33_AF3_MBGNT            (0x3 << 2)
#define GPIO_34_AF3_SSPSCLK3         (0x3 << 4)
#define GPIO_35_AF3_SSPTXD3          (0x3 << 6)
#define GPIO_36_AF3_KPMKIN7          (0x3 << 8)
#define GPIO_37_AF3_KPMKIN3          (0x3 << 10)
#define GPIO_38_AF3                  (0x3 << 12)
#define GPIO_39_AF3_SSPSFRM3         (0x3 << 14)
#define GPIO_40_AF3                  (0x3 << 16)
#define GPIO_41_AF3_SSPSRXD3         (0x3 << 18)
#define GPIO_42_AF3                  (0x3 << 20)
#define GPIO_43_AF3                  (0x3 << 22)
#define GPIO_44_AF3                  (0x3 << 24)
#define GPIO_45_AF3                  (0x3 << 26)
#define GPIO_46_AF3                  (0x3 << 28)
#define GPIO_47_AF3_PWMOUT3          (0x3 << 30)

/* 
 * GAFR1_U (gpio[63:48]) 
 */
/* AF1 */
#define GPIO_48_AF1_BBOBDAT1      (0x1 << 0)
#define GPIO_49_AF1               (0x1 << 2)
#define GPIO_50_AF1_BBOBDAT2      (0x1 << 4)
#define GPIO_51_AF1_BBOBDAT3      (0x1 << 6)
#define GPIO_52_AF1_BBOBCLK       (0x1 << 8)
#define GPIO_53_AF1_BBOBSTB       (0x1 << 10)
#define GPIO_54_AF1               (0x1 << 12)
#define GPIO_55_AF1               (0x1 << 14)
#define GPIO_56_AF1_PCMCIAnPWAIT  (0x1 << 16)
#define GPIO_57_AF1_PCMCIAnIOIS16 (0x1 << 18)
#define GPIO_58_AF1               (0x1 << 20)
#define GPIO_59_AF1               (0x1 << 22)
#define GPIO_60_AF1               (0x1 << 24)
#define GPIO_61_AF1               (0x1 << 26)
#define GPIO_62_AF1               (0x1 << 28)
#define GPIO_63_AF1               (0x1 << 30)

/* AF2 */
#define GPIO_48_AF2_PCMCIAnPOE           (0x2 << 0)
#define GPIO_49_AF2_nPWE                 (0x2 << 2)
#define GPIO_50_AF2_PCMCIAnPIOR          (0x2 << 4)
#define GPIO_51_AF2_PCMCIAnPIOW          (0x2 << 6)
#define GPIO_52_AF2_SSPSCLK3             (0x2 << 8)
#define GPIO_53_AF2                      (0x2 << 10)
#define GPIO_54_AF2_BBOBWAIT_PCMCIAnPCE2 (0x2 << 12)
#define GPIO_55_AF2_BBIBDAT1_PCMCIAnPREG (0x2 << 14)
#define GPIO_56_AF2_BBIBDAT2             (0x2 << 16)
#define GPIO_57_AF2_BBIBDAT3             (0x2 << 18)
#define GPIO_58_AF2_LDD0                 (0x2 << 20)
#define GPIO_59_AF2_LDD1                 (0x2 << 22)
#define GPIO_60_AF2_LDD2                 (0x2 << 24)
#define GPIO_61_AF2_LDD3                 (0x2 << 26)
#define GPIO_62_AF2_LDD4                 (0x2 << 28)
#define GPIO_63_AF2_LDD5                 (0x2 << 30)

/* AF3 */
#define GPIO_48_AF3     (0x3 << 0)
#define GPIO_49_AF3     (0x3 << 2)
#define GPIO_50_AF3     (0x3 << 4)
#define GPIO_51_AF3     (0x3 << 6)
#define GPIO_52_AF3     (0x3 << 8)
#define GPIO_53_AF3     (0x3 << 10)
#define GPIO_54_AF3     (0x3 << 12)
#define GPIO_55_AF3     (0x3 << 14)
#define GPIO_56_AF3     (0x3 << 16)
#define GPIO_57_AF3     (0x3 << 18)
#define GPIO_58_AF3     (0x3 << 20)
#define GPIO_59_AF3     (0x3 << 22)
#define GPIO_60_AF3     (0x3 << 24)
#define GPIO_61_AF3     (0x3 << 26)
#define GPIO_62_AF3     (0x3 << 28)
#define GPIO_63_AF3     (0x3 << 30)

/* 
 * GAFR2_L (gpio[79:64]) 
 */
/* AF1 */
#define GPIO_64_AF1               (0x1 << 0)
#define GPIO_65_AF1               (0x1 << 2)
#define GPIO_66_AF1               (0x1 << 4)
#define GPIO_67_AF1               (0x1 << 6)
#define GPIO_68_AF1               (0x1 << 8)
#define GPIO_69_AF1               (0x1 << 10)
#define GPIO_70_AF1               (0x1 << 12)
#define GPIO_71_AF1               (0x1 << 14)
#define GPIO_72_AF1               (0x1 << 16)
#define GPIO_73_AF1               (0x1 << 18)
#define GPIO_74_AF1               (0x1 << 20)
#define GPIO_75_AF1               (0x1 << 22)
#define GPIO_76_AF1               (0x1 << 24)
#define GPIO_77_AF1               (0x1 << 26)
#define GPIO_78_AF1_PCMCIAnPCE2   (0x1 << 28)
#define GPIO_79_AF1_PCMCIAPSKTSEL (0x1 << 30)

/* AF2 */
#define GPIO_64_AF2_LDD6      (0x2 << 0)
#define GPIO_65_AF2_LDD7      (0x2 << 2)
#define GPIO_66_AF2_LDD8      (0x2 << 4)
#define GPIO_67_AF2_LDD9      (0x2 << 6)
#define GPIO_68_AF2_LDD10     (0x2 << 8)
#define GPIO_69_AF2_LDD11     (0x2 << 10)
#define GPIO_70_AF2_LDD12     (0x2 << 12)
#define GPIO_71_AF2_LDD13     (0x2 << 14)
#define GPIO_72_AF2_LDD14     (0x2 << 16)
#define GPIO_73_AF2_LDD15     (0x2 << 18)
#define GPIO_74_AF2_LFCLKRD   (0x2 << 20)
#define GPIO_75_AF2_LLCLKA0   (0x2 << 22)
#define GPIO_76_AF2_LPCLKWR   (0x2 << 24)
#define GPIO_77_AF2_LBIAS     (0x2 << 26)
#define GPIO_78_AF2_nCS2      (0x2 << 28)
#define GPIO_79_AF2_nCS3      (0x2 << 30)

/* AF3 */
#define GPIO_64_AF3           (0x3 << 0)
#define GPIO_65_AF3           (0x3 << 2)
#define GPIO_66_AF3           (0x3 << 4)
#define GPIO_67_AF3           (0x3 << 6)
#define GPIO_68_AF3           (0x3 << 8)
#define GPIO_69_AF3           (0x3 << 10)
#define GPIO_70_AF3           (0x3 << 12)
#define GPIO_71_AF3           (0x3 << 14)
#define GPIO_72_AF3           (0x3 << 16)
#define GPIO_73_AF3           (0x3 << 18)
#define GPIO_74_AF3           (0x3 << 20)
#define GPIO_75_AF3           (0x3 << 22)
#define GPIO_76_AF3           (0x3 << 24)
#define GPIO_77_AF3           (0x3 << 26)
#define GPIO_78_AF3           (0x3 << 28)
#define GPIO_79_AF3           (0x3 << 30)

/* 
 * GAFR2_U (gpio[95:80]) 
 */
/* AF1 */
#define GPIO_80_AF1_DREQ1       (0x1 << 0)
#define GPIO_81_AF1_SSPTXD3     (0x1 << 2)
#define GPIO_82_AF1_SSPRXD3     (0x1 << 4)
#define GPIO_83_AF1_SSPSFRM3    (0x1 << 6)
#define GPIO_84_AF1             (0x1 << 8)
#define GPIO_85_AF1_PCMCIAnPCE1 (0x1 << 10)
#define GPIO_86_AF1             (0x1 << 12)
#define GPIO_87_AF1             (0x1 << 14)
#define GPIO_88_AF1_USBHPWR0    (0x1 << 16)
#define GPIO_89_AF1_AC97SYSCLK  (0x1 << 18)
#define GPIO_90_AF1_KPMKIN5     (0x1 << 20)
#define GPIO_91_AF1_KPMKIN6     (0x1 << 22)
#define GPIO_92_AF1_MMDAT0      (0x1 << 24)
#define GPIO_93_AF1_KPDKIN0     (0x1 << 26)
#define GPIO_94_AF1_KPDKIN1     (0x1 << 28)
#define GPIO_95_AF1_KPDKIN2     (0x1 << 30)

/* AF2 */
#define GPIO_80_AF2_MBREQ_nCS4  (0x2 << 0)
#define GPIO_81_AF2_BBOBDAT0    (0x2 << 2)
#define GPIO_82_AF2_BBIBDAT0    (0x2 << 4)
#define GPIO_83_AF2_BBIBCLK     (0x2 << 6)
#define GPIO_84_AF2_BBIBSTB     (0x2 << 8)
#define GPIO_85_AF2_BBIBWAIT    (0x2 << 10)
#define GPIO_86_AF2_LDD16       (0x2 << 12)
#define GPIO_87_AF2_LDD17       (0x2 << 14)
#define GPIO_88_AF2             (0x2 << 16)
#define GPIO_89_AF2_USBHPEN0    (0x2 << 18)
#define GPIO_90_AF2_URST        (0x2 << 20)
#define GPIO_91_AF2_UCLK        (0x2 << 22)
#define GPIO_92_AF2_MSBS        (0x2 << 24)
#define GPIO_93_AF2             (0x2 << 26)
#define GPIO_94_AF2             (0x2 << 28)
#define GPIO_95_AF2             (0x2 << 30)

/* AF3 */
#define GPIO_80_AF3             (0x3 << 0)
#define GPIO_81_AF3             (0x3 << 2)
#define GPIO_82_AF3             (0x3 << 4)
#define GPIO_83_AF3             (0x3 << 6)
#define GPIO_84_AF3             (0x3 << 8)
#define GPIO_85_AF3             (0x3 << 10)
#define GPIO_86_AF3             (0x3 << 12)
#define GPIO_87_AF3             (0x3 << 14)
#define GPIO_88_AF3             (0x3 << 16)
#define GPIO_89_AF3             (0x3 << 18)
#define GPIO_90_AF3             (0x3 << 20)
#define GPIO_91_AF3             (0x3 << 22)
#define GPIO_92_AF3             (0x3 << 24)
#define GPIO_93_AF3             (0x3 << 26)
#define GPIO_94_AF3             (0x3 << 28)
#define GPIO_95_AF3             (0x3 << 30)

/* 
 * GAFR3_L (gpio[111:96]) 
 */
/* AF1 */
#define GPIO_96_AF1_KPDKIN3            (0x1 << 0)
#define GPIO_97_AF1_KPDKIN4            (0x1 << 2)
#define GPIO_98_AF1_KPDKIN5_AC97SYSCLK (0x1 << 4)
#define GPIO_99_AF1_KPDKIN6            (0x1 << 6)
#define GPIO_100_AF1_KPMKIN0           (0x1 << 8)
#define GPIO_101_AF1_KPMKIN1           (0x1 << 10)
#define GPIO_102_AF1_KPMKIN2           (0x1 << 12)
#define GPIO_103_AF1                   (0x1 << 14)
#define GPIO_104_AF1                   (0x1 << 16)
#define GPIO_105_AF1                   (0x1 << 18)
#define GPIO_106_AF1                   (0x1 << 20)
#define GPIO_107_AF1                   (0x1 << 22)
#define GPIO_108_AF1_CHOUT0            (0x1 << 24)
#define GPIO_109_AF1_MMDAT1            (0x1 << 26)
#define GPIO_110_AF1_MMDAT2            (0x1 << 28)
#define GPIO_111_AF1_MMDAT3            (0x1 << 30)

/* AF2 */
#define GPIO_96_AF2_MBREQ_DVAL1        (0x2 << 0)
#define GPIO_97_AF2_DREQ1_MBGNT        (0x2 << 2)
#define GPIO_98_AF2                    (0x2 << 4)
#define GPIO_99_AF2_AC97SDATAIN1       (0x2 << 6)
#define GPIO_100_AF2                   (0x2 << 8)
#define GPIO_101_AF2                   (0x2 << 10)
#define GPIO_102_AF2                   (0x2 << 12)
#define GPIO_103_AF2_KPMKOUT0          (0x2 << 14)
#define GPIO_104_AF2_KPMKOUT1          (0x2 << 16)
#define GPIO_105_AF2_KPMKOUT2          (0x2 << 18)
#define GPIO_106_AF2_KPMKOUT3          (0x2 << 20)
#define GPIO_107_AF2_KPMKOUT4          (0x2 << 22)
#define GPIO_108_AF2_KPMKOUT5          (0x2 << 24)
#define GPIO_109_AF2_MSSDIO            (0x2 << 26)
#define GPIO_110_AF2                   (0x2 << 28)
#define GPIO_111_AF2                   (0x2 << 30)

/* AF3 */
#define GPIO_96_AF3                    (0x3 << 0)
#define GPIO_97_AF3_KPMKIN3            (0x3 << 2)
#define GPIO_98_AF3_KPMKIN4            (0x3 << 4)
#define GPIO_99_AF3_KPMKIN5            (0x3 << 6)
#define GPIO_100_AF3                   (0x3 << 8)
#define GPIO_101_AF3                   (0x3 << 10)
#define GPIO_102_AF3                   (0x3 << 12)
#define GPIO_103_AF3                   (0x3 << 14)
#define GPIO_104_AF3                   (0x3 << 16)
#define GPIO_105_AF3                   (0x3 << 18)
#define GPIO_106_AF3                   (0x3 << 20)
#define GPIO_107_AF3                   (0x3 << 22)
#define GPIO_108_AF3                   (0x3 << 24)
#define GPIO_109_AF3                   (0x3 << 26)
#define GPIO_110_AF3                   (0x3 << 28)
#define GPIO_111_AF3                   (0x3 << 30)

/* 
 * GAFR3_U (gpio[120:112]) 
 */
/* AF1 */
#define GPIO_112_AF1_MMCMD      (0x1 << 0)
#define GPIO_113_AF1_I2SSYSCLK  (0x1 << 2)
#define GPIO_114_AF1            (0x1 << 4)
#define GPIO_115_AF1_DREQ0      (0x1 << 6)
#define GPIO_116_AF1_DVAL0      (0x1 << 8)
#define GPIO_117_AF1_SCL        (0x1 << 10)
#define GPIO_118_AF1_SDA        (0x1 << 12)
#define GPIO_119_AF1_USBHPWR1   (0x1 << 14)
#define GPIO_120_AF1            (0x1 << 16)

/* AF2 */
#define GPIO_112_AF2_MSINS      (0x2 << 0)
#define GPIO_113_AF2_AC97nRESET (0x2 << 2)
#define GPIO_114_AF2_UVS0       (0x2 << 4)
#define GPIO_115_AF2_nUVS1      (0x2 << 6)
#define GPIO_116_AF2_nUVS2      (0x2 << 8)
#define GPIO_117_AF2            (0x2 << 10)
#define GPIO_118_AF2            (0x2 << 12)
#define GPIO_119_AF2            (0x2 << 14)
#define GPIO_120_AF2_USBHPEN1   (0x2 << 16)

/* AF3 */
#define GPIO_112_AF3            (0x3 << 0)
#define GPIO_113_AF3            (0x3 << 2)
#define GPIO_114_AF3            (0x3 << 4)
#define GPIO_115_AF3_MBREQ      (0x3 << 6)
#define GPIO_116_AF3_MBGNT      (0x3 << 8)
#define GPIO_117_AF3            (0x3 << 10)
#define GPIO_118_AF3            (0x3 << 12)
#define GPIO_119_AF3            (0x3 << 14)
#define GPIO_120_AF3            (0x3 << 16)

/* Nam9, 2004. 9. 3 */

#define ICPR  __REG(INTC_BASE_PHYSICAL + 0x10)
//#define UDCCR  __REG(PERIF_BASE_PHYSICAL + UDC_OFFSET)
#define CKEN            __REG( CLK_BASE_PHYSICAL + CKEN_OFFSET )
#define CKEN11_USB (CKEN11_USBDEV) /* USB Client Clock Enable */
#define UDCCS0_OPR (1 << 0)
#define UDCCS0_SA (1 << 7)

/* Bulverde USB register's definition */
#define UDCCR        __REG(0x40600000)
#define UDCICR0      __REG(0x40600004)
#define UDCICR1      __REG(0x40600008)
#define UDCISR0      __REG(0x4060000c)
#define UDCISR1      __REG(0x40600010)
#define UDCFNR       __REG(0x40600014)
#define UP2OCR       __REG(0x40600020)

#define UDCCSR0      __REG(0x40600100)
#define UDCCSRA      __REG(0x40600104)
#define UDCCSRB      __REG(0x40600108)
/* Omit endpoint C~X */

#define UDCBCR0      __REG(0x40600200)
#define UDCBCRA      __REG(0x40600204)
#define UDCBCRB      __REG(0x40600208)
/* Omit endpoint C~X */

#define UDCDR0       __REG(0x40600300)
#define UDCDRA       __REG(0x40600304)
#define UDCDRB       __REG(0x40600308)
#define UDCWAKEUP    __REG(0x40F00044)

/* Omit endpiont C~X */

#define UDCCRA       __REG(0x40600404)
#define UDCCRB       __REG(0x40600408)
/* Omit endpoint C~X */

/* USB register bit definitions */

#define UDCCR_UDE    (1 << 0)
#define UDCCR_UDA    (1 << 1)
#define UDCCR_UDR    (1 << 2)
#define UDCCR_EMCE   (1 << 3)
#define UDCCR_SMAC   (1 << 4)
#define UDCCR_AAISN  (1 << 5)
/* Nam9 */
#define UDCCR_SRM    (1 << 5)
#define UDCCR_REM    (1 << 7)
#define UDCCR_AIN    (1 << 8)
#define UDCCR_ACN    (1 << 11)
#define UDCCR_DWRE   (1 << 16)

#define UDCICR0_IE0  (1 << 0)
#define UDCICR0_IEA  (1 << 2)
#define UDCICR0_IEB  (1 << 4)
/* Omit endpoint C~X */

#define UDCICR1_IERS (1 << 27)
#define UDCICR1_IESU (1 << 28)
#define UDCICR1_IERU (1 << 29)
#define UDCICR1_IESOF (1 << 30)
#define UDCICR1_IECC (1 << 31)

#define UDCISR0_IR0  (1 << 0)
#define UDCISR0_IRA  (1 << 2)
#define UDCISR0_IRB  (1 << 4)
/* Omit endpiont C~X */

#define UDCISR1_IRRS (1 << 27)
#define UDCISR1_IRSU (1 << 28)
#define UDCISR1_IRRU (1 << 29)
#define UDCISR1_IRSOF (1 << 30)
#define UDCISR1_IRCC (1 << 31)

#define UDCCSR0_OPC  (1 << 0)
#define UDCCSR0_IPR  (1 << 1)
#define UDCCSR0_FTF  (1 << 2)
#define UDCCSR0_DME  (1 << 3)
#define UDCCSR0_SST  (1 << 4)
#define UDCCSR0_FST  (1 << 5)
#define UDCCSR0_RNE  (1 << 6)
#define UDCCSR0_SA   (1 << 7)

#define UDCCSR_FS    (1 << 0)
#define UDCCSR_PC    (1 << 1)
#define UDCCSR_TRN   (1 << 2)
#define UDCCSR_DME   (1 << 3)
#define UDCCSR_SST   (1 << 4)
#define UDCCSR_FST   (1 << 5)
#define UDCCSR_BNE   (1 << 6)
#define UDCCSR_BNF   (1 << 6)
#define UDCCSR_SP    (1 << 7)
#define UDCCSR_FEF   (1 << 8)
#define UDCCSR_DPE   (1 << 9)

#define UDCCRB_EE    (1 << 0)
#define UDCCRB_DE    (1 << 1)
#define UDCCRB_MPS   (1 << 2)
#define UDCCRB_ED    (1 << 12)
#define UDCCRB_ET    (1 << 13)
#define UDCCRB_EN    (1 << 15)
#define UDCCRB_AISN  (1 << 19)
#define UDCCRB_IN    (1 << 22)
#define UDCCRB_CN    (1 << 25)

#endif // _BL_BULVERDE_H_
